The present invention relates to a semiconductor device having a capacitor using a ferroelectric layer or dielectric layer having high permittivity as a capacitor insulating layer.
Recently, to realize a nonvolatile RAM of low operating voltage and capable of writing/reading at high speed never known before, technical developments are intensively attempted to form a capacitor using a ferroelectric layer having spontaneous polarization as a capacitor insulating layer, on a semiconductor integrated circuit. At the same time, as the consumer electronic appliances are becoming higher in density, unwanted radiation which is electromagnetic noise released from electronic appliances is posing a serious problem. As the measure to reduce the unwanted radiation, a keen attention has been concentration on the technology of incorporating a capacitor of large capacitance using a ferroelectric layer or a dielectric layer having high permittivity (these layers are commonly called high permittivity dielectric layer hereinafter) as a capacitor insulating layer, into a semiconductor integrated circuit.
A conventional semiconductor device having a capacitor is described below while referring to FIG. 6. An isolation oxide layer 2 is formed on a silicon substrate 1, and a transistor 5 composed of a diffusion layer 3, a gate insulating layer 4a and a gate electrode 4b is formed in a region surrounded by the isolation oxide layer 2. An insulating layer 6 to cover the transistor 5 is formed, and a capacitor 10 composed of a bottom electrode 7, a capacitor insulating layer 8 and a top electrode 9 is formed on the insulating layer 6. The capacitor insulating layer 8 is processed in a same shape as the top electrode 9, and the end portion of the capacitor insulating layer 8 is exactly at the same position of the end portion of the top electrode 9, or at a position of nearly with outside 0.1 .mu.m if the processing precision is taken into consideration. The end portion of the capacitor insulating layer 8 is inside of the end portion or the bottom electrode 7.
To cover the capacitor 10, further, a passivation layer 11 composed of a silicon oxide layer containing phosphorus is formed. Contact holes 12a reaching the diffusion layer 3, and contact holes 12b reaching the bottom electrode 7 and top electrode 9 are formed in the insulating layer 6 and passivation layer 11. Interconnections 13a, 13b are formed through these contact holes 12a, 12b.
In such conventional structure, however, the following problems occur. That is, the end portion of the capacitor insulating layer 8 is likely to be damaged when patterning into a shape of capacitor by dry etching or the like, or it may react with the passivation layer 11 when forming the passivation layer 11. As a result, the crystallinity of the end portion of the capacitor insulating layer 8 deteriorates. Therefore, in the conventional structure in which the capacitor insulating layer 8 and top electrode 9 are identical in shape, the degraded crystallinity portion is contained in the capacitor, and it is likely to cause deterioration of electric characteristics, such as drop of capacitance, increase of leakage current, and drop of dielectric strength.